The invention relates to a method for fabricating a power transistor arrangement and to a method for fabricating a power transistor arrangement with a transistor edge termination. The invention also relates to a power transistor arrangement.
Transistor arrangements in the form of MOS (Metal Oxide Semiconductor) power transistors are provided for controlling switching currents at high current levels (up to several 10s of amps) using low control voltages. The withstand voltage of such power transistors may be up to several 100 V. The switching times are usually in the region of a few microseconds.
MOS power transistors are available in the form of trench MOS power transistors, for example. A trench MOS power transistor is formed in a semiconductor substrate which has a respective plurality of trench transistor cells arranged next to one another in at least one active cell array.
Depending on the design of the trench transistor cells, it is possible to provide normally-on and normally-off p-channel or n-channel trench MOS power transistors, for example.
FIG. 1 shows a conventional power transistor arrangement 1, in the form of a trench MOS power transistor, with a schematic illustration of the source, drain and gate connections, said power transistor being in the form of an n-channel MOSFET with a vertical, double-diffused trench structure (VDMOSFET, vertical double-diffused metal oxide semiconductor field effect transistor). In this case, a drain metallization 231 connected to the drain connection is arranged on the back of a semiconductor substrate 16. The drain metallization 231 is adjoined in the semiconductor substrate 16 by an n++-doped drain layer 23. Opposite the drain metallization 231, the drain layer 23 is adjoined by a drift zone 232. The drift zone 232 is generally formed from a weakly n-doped portion of the semiconductor substrate 16, which is normally made of epitaxially applied silicon. When the trench MOS power transistor is in off-state mode, a space-charge zone whose extent essentially determines the maximum reverse voltage develops in the drift zone 232.
A cell array 3 contains cell array trenches 5 in the semiconductor substrate 16. In this example, the cell array trenches 5, which are shown in cross section, extend parallel in one direction at right angles to the cross-sectional face. The cell array trenches 5 contain gate electrode structures 10 and field electrode structures 11. The field electrode structure 11 is insulated from the semiconductor substrate 16 by an insulating layer 18 which is formed from a field oxide. The gate electrode structure 10 is insulated from the field electrode structure 11 and the semiconductor substrate 16 by a gate insulating layer 20 made of silicon oxide. The drift zone 232 of the semiconductor substrate 16 is adjoined in regions between the cell array trenches 5 by p-doped body zones which are opposite the gate electrode structures 10.
Provided between the body zones and a substrate surface 17 are n++-doped source regions 8a. The field electrode structures 11 reduce a parasitic capacitance between the gate electrode structures 10 and the drift zone 232. Source contact trenches 8 are used to provide electrically conductive connections between a source metallization 15 and the source regions 8a. The source metallization 15 is electrically insulated from the gate electrode structures 10 by an intermediate oxide layer 22. The material both of the gate electrode structures 10 and of the field electrode structures 11 is highly doped polysilicon, for example. The conductivity of the gate electrode structure 10 may be improved by an additional layer in the gate electrode structure 10, for example a silicide layer. The cell array trench 5 with the gate electrode structure 10 and the field electrode structure 11 forms, together with the adjoining, doped regions of the semiconductor substrate 16, a trench transistor cell 2, which extends as far as the drain layer 23.
If the gate electrode structure 10 in an active trench transistor cell 2 of this type has a positive potential applied to it, then an n-conductive inversion channel forms in the p-doped body zone from the p-doped body zone's minority carriers (electrons) which are enriched there.
In an edge region 4 of the power transistor arrangement 1 in the form of a trench MOS power transistor, contact is made firstly between the field electrode structures 11 arranged in the cell array trenches 5 and the source metallization 15, and secondly contact is made between the gate electrode structures 10 arranged in the cell array trenches 5 and a gate metallization 14. In addition, an example of a shielding electrode 12 is shown in the edge region 4.
The contact between the field electrode structures 11 arranged in the cell array trenches 5 is made in a cross-sectional plane VII which is parallel to the cross-sectional plane VI. In the cell array trenches 5 running at right angles to the cross-sectional plane VI, the gate electrode structures 10 do not extend over the entire length of the cell array trenches 5, which means that contact with the respective field electrode structure 11 is made in a connecting region of the cell array trenches 5, as shown in the plane VII. Each field electrode structure 11 drawn over the substrate surface 17 is electrically conductively connected to the source metallization 15.
In a further cross-sectional plane VIII, extending between the first cross-sectional plane VI and the second cross-sectional plane VII and parallel to the latter, the gate electrode structures 10 are electrically connected to an edge gate structure 13. The edge gate structure 13 is electrically conductively connected to the gate metallization 14. The edge gate structures 13 and the shielding electrodes 12 are formed from doped polysilicon. The source metallization 15, the gate metallization 14, the edge gate structure 13, the shielding electrode 12 and the semiconductor substrate 16 are respectively insulated from one another by an insulating layer 18, an intermediate oxide layer 22 and a further insulating layer 18.
To fabricate a complex structure, such as the power transistor arrangement described in FIG. 1, in which both the gate electrode structure and the field electrode structure are routed out into the edge region, where they are respectively connected to a gate metallization, or to a source metallization, at least seven patterning planes are required in currently known fabrication methods.
A patterning plane comprises a lithographical mapping of structures prescribed on an exposure mask onto the semiconductor substrate which is to be patterned, followed by etching, deposition or growth and planarization steps.
The at least seven patterning planes for fabricating a power transistor arrangement, in line with FIG. 1, comprise a trench patterning, where cell array and edge trenches are made in the semiconductor substrate, patterning of deposited polysilicon in order to form the field electrode structure,                patterning of a gate insulating layer (gate oxide), patterning of a second deposited polysilicon layer to form the gate electrode structure, patterning of body and source regions, patterning of contact holes and patterning of a metal plane.        
A great cost factor in each patterning plane is the lithographical mapping, since the appliances needed for this are technically very complex and cost intensive. In addition, the entire mapping process requires high precision and is thus very susceptible to error. For the reasons mentioned, attempts are made to reduce the number of lithographical mapping operations and hence also the number of patterning planes.
Methods are proposed which require only five and only four patterning planes. In the case of the method with five patterning planes, the body and source patterning and also gate electrode patterning planes are eliminated. Lithographical mapping operations are then no longer used either for the body and source patterning or for the gate electrode patterning. The remaining five patterning planes comprise the trench patterning, the field electrode patterning, the patterning of the gate insulating layer, the contact hole patterning and the patterning of the metal plane.
The method with four patterning planes involves the patterning of the field electrode structure and the patterning of the gate insulating layer being combined into one patterning plane. However, the lithographical mapping in this patterning plane makes great demands on alignment tolerance and CD (critical dimension).
The present invention is based on the object of providing an inexpensive method having an even more reduced number of patterning planes for fabricating a power transistor arrangement. The object covers a method for fabricating a power transistor arrangement having a transistor edge termination, and a power transistor arrangement fabricated using the method.